In many types of non-volatile memory (NVM) cells, such as flash memory or electrically erasable, programmable read only memory (EEPROM), an example of which is a nitride, read only memory (NROM), reading data stored in the memory cell should be performed at a known minimum VDD voltage. For example, but not necessarily, the read voltage should be not less than 2.4V. Below this voltage, charge pump circuits, sense amplifiers, regulator circuits, and the NROM cell itself may not function properly, resulting in incorrect data and margin loss. Thus, it is desirable that the circuitry (chip) should have internal circuit to detect that VDD has reached the required minimum value.
Reference is now made to FIG. 1, which illustrates a prior art circuit for detecting that VDD is greater than a minimum value (e.g., VDD>2.4V). This circuit is also called an accurate power-up comparator or accurate level comparator or accurate comparator. The circuit compares a reference voltage, BGREF (bandgap voltage reference), to a resistor divider 5 from VDD. The resistor divider 5 comprises two resistors R1 and R2 connected in series at a node n1. The comparator comprises a differential pair of NMOS (n-channel metal oxide semiconductor) transistors M1 and M2, a tail current source I1, and a current mirror (active load) that includes PMOS (p-channel metal oxide semiconductor) transistors M4 and M5.
In the current mirror (active load), the gates of PMOS transistors M4 and M5 are connected to each other, and the drain of PMOS transistor M5 is connected to its gate. The sources of PMOS transistors M4 and M5 may be connected to a reference voltage, such as VDD.
The gate of NMOS transistor M2 is connected to BGREF, whereas the gate of NMOS transistor M1 is connected to node n1. The sources of NMOS transistors M1 and M2 are connected to current source I1. The drain of NMOS transistor M2 is connected to the drain of PMOS transistor M4 via a node n2 and the drain of NMOS transistor M1 is connected to the drain of PMOS transistor M5 via a node n3.
Two inverters 6 and 7 buffer the comparator output OPC (from node n2) to the general output OP. Inverter 6 is connected to the drain of PMOS transistor M4 via node n2 and the output of inverter 7 is connected to the input of inverter 6.
In this particular example, the value of resistor R1 is identical to that of resistor R2, and BGREF equals 1.2V. For these values, the node OPC is at a low voltage, close to GND for VDD<2.4. When VDD>2.4V, node n1 is greater than BGREF, and the current in NMOS transistor M1 is greater than the current in NMOS transistor M2. The current in NMOS transistor M1 is mirrored from PMOS transistor M5 to PMOS transistor M4, which forces the comparator output OPC to a high state, close to VDD. The inverters 6 and 7 buffer this signal to the general output OP, which is a logical signal indicating that VDD>2.4 when it is high.
In order to function properly, the accurate comparator assumes that BGREF is at a stable voltage, meaning that VDD is sufficiently high to allow BGREF to function.
Reference is now made to FIG. 2, which illustrates a prior art BGREF circuit. The BGREF circuit is connected to power-up circuit 8 (also referred to as start-up circuitry or a BGREF level comparator), used to indicate that VDD has reached a level at which BGREF can operate. Power-up circuit 8 is shown and described hereinbelow with reference to FIG. 3.
The illustrated BGREF circuit comprises three branches, headed by PMOS transistors XA1A, XA1B and XA1C, whose sources are all connected to VDD. PMOS transistors XA1A and XA1B form a current mirror, wherein the gates of PMOS transistors XA1A and XA1B are connected together and the drain of PMOS transistor XA1B is connected to its gate. The gate of PMOS transistor XA1A is connected to the power-up circuit 8. The drains of PMOS transistors XA1A and XA1B are connected to the drains of NMOS transistors XA2A and XA2B.
NMOS transistors XA2A and XA2B form a current mirror, wherein the gates of NMOS transistors XA2A and XA2B are connected together and the drain of NMOS transistor XA2A is connected to its gate, which is also connected to the power-up circuit 8. The source of NMOS transistor XA2A is connected to a diode D1. The source of NMOS transistor XA2B is connected to a diode D2 via a resistor R1.
The gate of PMOS transistors XA1C is connected to the gate of PMOS transistor XA1B. The drain of PMOS transistor XA1C is connected to a diode D3 via a resistor R2. The output of the BGREF circuit is designated as OP.
As is known in the art, in order for the BGREF circuit to turn on, VDD must be sufficiently high for each transistor and diode in the circuit to turn on. For a transistor to turn on, its Vgs (gate-source voltage) must be above Vtn (threshold for NMOS) or Vtp (threshold for PMOS), which may be 0.7V (although not necessarily this value). The Vtn and Vtp parameters are very process dependent and can vary independently of each other. The transistor Vgs must have sufficient overdrive (Vdsat), which may be 0.2V, to drive its current. The transistor Vds (drain-source) voltage must be above Vdsat to be in the saturation regime. The diode voltages must be above Vd, which may be 0.7V.
Thus in the branch of PMOS transistor XA1A, VDD must be above Vtn+Vd+2*Vdsat. For the PMOS transistor XA1B branch, VDD>Vtp+Vd+2*Vdsat. In the output branch of PMOS transistor XA1C, the output should be at 1.2V, thus VDD>1.2V +Vdsat. It is apparent that Vtn, Vtp, and Vd all may play a critical role in determining the minimum supply voltage of the BGREF.
Reference is now made to FIG. 3, which illustrates a prior-art power-up circuit, used to indicate that VDD has reached a level at which BGREF can operate. The circuit may be identical to that of FIG. 1, except that the gate of NMOS transistor M2 is connected to the gate of an NMOS transistor M3. The NMOS transistors M2 and M3 form a current mirror in the more general meaning, wherein the drain of NMOS transistor M3 is connected to its gate but the source of M3 is connected to ground, while as mentioned above the source of M2 can be connected to a current source I1. The drain of NMOS transistor M3 is connected to a current source I2 at a node n4. The current source I2 may be connected to a reference voltage, such as VDD.
The circuitry of FIG. 3 compares Vtn of NMOS transistor M3 to VDD divided by the resistor divider 5. The comparator output flips, trips or changes state when VDD is a multiple of Vtn. The resistor divider 5 can be scaled such that the trip point of the comparator is close to the operating VDD of the BGREF circuit in FIG. 2. This trip point is typically between 1.6V and 2.3V. The trip point can be designed to be arbitrarily large, by changing the resistor divider 5. However, it is necessary to keep the trip point sufficiently below the minimum operating VDD voltage of the chip.
It is clear that the circuit of FIG. 3 depends only on Vtn, while the operating VDD voltage of the BGREF in FIG. 2 depends on the Vtn, Vtp, and Vd. Thus, there are situations where Vtn is small and Vtp, Vd are large. In these cases, the comparator flips at a voltage where BGREF is not yet ready. This can result in the accurate comparator giving an erroneous reading, resulting in an incorrect first read.